1. Technical Field
Embodiments of the present disclosure relate to a layout structure of a semiconductor memory device including a sub wordline driver.
2. Related Art
A semiconductor memory device may write or read data in or from memory cells coupled to word lines and bit lines. The memory cells coupled to the word lines may form one row such that the respective memory cells can operate according to a voltage applied to the word lines.
With increasing storage capacity of semiconductor memory devices, a speed delay problem has arisen in which a word line voltage applied to one word line is applied to a plurality of memory cells.
In order to address the speed delay problem, there has been proposed an improved scheme in which one word line is divided into a plurality of sub wordlines and each sub wordline is driven by a sub wordline driver (SWD).